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-- Company: 
-- Engineer: 
-- 
-- Create Date:    19:27:31 11/20/2011 
-- Design Name: 
-- Module Name:    latch2 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity latch2 is
    port (
        i      : in  std_ulogic_vector(1 downto 0);
        o      : out std_ulogic_vector(1 downto 0);
        clk    : in  std_ulogic;
        rst    : in  std_ulogic;
        enable : in  std_ulogic
        );
end latch2;

architecture Behavioral of latch2 is
    component latch
        port (
            i      : in  std_ulogic;
            o      : out std_ulogic;
            clk    : in  std_ulogic;
            rst    : in  std_ulogic;
            enable : in  std_ulogic
            );
    end component;

begin

    U0 : latch port map(i(0), o(0), clk, rst, enable);
    U1 : latch port map(i(1), o(1), clk, rst, enable);

end Behavioral;

